The present invention relates to methods for analyzing integrated circuits (ICs) during design of those ICs or during the failure analysis of those ICs during development. More particularly, present invention relates to a new and improved method of automatically identifying points or locations within an IC which are the likely cause of a failure or malfunction of the IC, under conditions where multiple output signals fail from the IC. The first above identified invention is utilized with the present improvements in defining, for each of the failed output signals, a logic cone or rearward extending group of only the relevant circuit components or cells of the IC which cause a particular output signal at a predetermined output signal transition time and the input signals to each relevant cell that predict the functionality of that cell in the cone. A logic cone will be generated for each of the failing output signals from the IC, and the convergence point of the logic cones should represent the approximate location and component within the IC which causes the failure for all of the failed output signals. Analysis of the IC is facilitated by reducing the amount of time and the tedium required for tracing design and defect circuit failures.
Most modern semiconductor integrated circuits (ICs) are extremely complex in the number and interconnection of their components or cells. The complexity results from a number of trends in modern electronics. For example, the continual miniaturization of ICs allows more functional cells to be placed on the same sized chip for essentially no additional cost. The cost of an IC is generally related only to the physical size of the substrate upon which the IC is formed and not to the number of components of the IC. Therefore, the effort is to include more cells and functionality in each new IC. The trend in electronics has also been toward integrating entire systems into a single chip, or at least toward integrating larger portions of entire systems into single chips. Such ICs are called application-specific integrated circuits (ASICS) or system level integrated circuits (SLICs).
Fabricating a modern, complex IC, such as an ASIC or SLIC, is also a complicated task. The fabrication involves designing the schematic circuitry by using specific cells and connecting them in certain manner, and then simulating the functionality of the schematic circuitry to determine whether the circuitry meets the desired functionality. The design and the simulation are so complex that both functions are generally performed by computer programs or tools designed for those specific purposes. For example, the circuit itself is designed by the use of a behavioral level language, which defines the all of cells in the circuit and their connectivity, and in doing so creates a file known as a netlist which describes those cells and their connectivity. A schematic viewing tool obtains information from the netlist to create a visual display of the circuit and its components. To test the functionality of the circuit, a Verilog simulation program is used. The Verilog simulation program refers to the netlist and additional information which defines the logical function and time delays and other functional factors associated with each of the cells, and develops output state change signals and output transition times for each of the cells in response to a specific input signal. The output state change signals and the output transition times for each of the cells is thereafter displayed by the use of a waveform viewing tool. The waveform viewing tool makes use of the output state change and transition time information derived from the Verilog simulation program to create a display of the waveforms existing at each of the cells in the circuit. The use of behavioral level language circuit synthesis tools and Verilog simulation tools is well-known.
The design and fabrication a semiconductor chip is very complex and usually requires a relatively long period of time, typically measured in months or years to complete. Like any other complex procedure, mistakes or anomalies may arise and prevent proper functionality. Any anomalies arising from fabrication, circuit design errors and oversights, and functional or logic errors must identified and corrected before the semiconductor chip is released for commercial use. The phase of the overall fabrication procedure during which these oversights and anomalies are identified and corrected is referred to as the xe2x80x9cdebugxe2x80x9d stage. It is essential that the design errors and fabrication anomalies be identified and corrected during the debug stage, because otherwise the IC will not achieve its intended functionality. Furthermore, until the errors are identified and understood, corrections may need to be made in the circuit design, the connectivity of the logic cells and/or the fabrication process, to eliminate the defects.
To identify the errors during the debug stage, it is typical to use testers which generate particular signals and combinations of signals that are applied to the fabricated IC, and to measure the response of the IC to these input stimulus signals. The responses are measured both at the output of the IC and internally at different connection points or nodes between the cells. The internal measurements are obtained either by the use of a mechanical probe which physically contacts a node or by an electron beam device which projects an electron beam onto the node and derives an electrical signal from the electron beam. The signals derived from the actual IC are then compared to the computer tool-simulated signals at the comparable nodes of the simulated schematic circuit. If there is a discrepancy, that discrepancy indicates a problem in the fabrication or design of the IC. Thus, the typical previous approach to identifying the errors is to first obtain the actually-measured signals from the IC under the conditions which create the error, and then compare the actually-measured signals to the signals generated from a waveform simulation based on the circuit schematic.
The large number of very small cells within the typical IC complicates the task of tracing the signal within the IC. The task is made even more difficult by the difficulty in locating particular nodes and cells among the hundreds or thousands of such nodes and cells in a typical IC. Moreover, the task can be further complicated if the engineer or technician who is involved in conducting the tests did not design the circuit. Under such circumstances the test engineer is not as familiar with the circuit design as the design engineer, which further complicates the task and increases the possibility of further inadvertent errors.
Moreover, the complexity arising from the number and connectivity of the cells makes it a very time-consuming task to debug the IC. The debug process begins by identifying the particular circumstances or combination of input signals which create the error. The error is manifested in an erroneous output signal delivered from an output pad of the IC. Knowing the output error signal allows the test engineer to work backward into the preceding logic cells within the IC in an orderly, step-by-step manner to attempt to locate the cells or nodes within the IC which give rise to the error. The error may be caused by any of a series of components through which the preceding signals pass to influence the later-occurring signals and the output signals. Thus, viewed from the rear of the circuit looking forward into the preceding logic cells and nodes of the IC, there is an ever expanding segment or xe2x80x9cconexe2x80x9d of logic cells which are possible candidates for generating the error.
To trace a cone of logic cells, it is typical to trace the circuit schematic diagram and identify the logic cells which may have created the error. The tracing occurs manually, by employing mental steps used by the test and debug engineer, aided by the circuit diagram and waveform diagrams presented by the schematic viewing and waveform viewing tools. After identifying the logic cells and connection nodes of those logic cells, the output signal from each of the relevant logic cells is manually obtained from the comparable nodes and cells on the fabricated IC. After obtaining the measured signals, they are compared to the simulated signals. Any discrepancy points to the cause of the error. The complexity of the circuit prevents any other logical approach to identifying the errors, other than working backwards manually in a step-by-step manner.
Days of time could be consumed in tracing the schematic diagram to identify the relevant components, collecting the measured signals from the IC, understanding the functionality of the circuit, and comparing the measured signals to the simulated signals. The task was complicated when the test engineer did not possess the same familiarity with the circuit schematic as did the original circuit designer. Such a circumstance sometimes occurs because of changes in personnel during the long time which can elapse between the circuit design phase of the IC and the fabrication phase of the IC. Furthermore, because of the complexity involved in the circuit and the necessity to use a manual, methodical and step-by-step approach to tracing the signals backwards through the circuit, it has been unproductive to guess or speculate as to the cause of an error without undertaking the step-by-step, methodical analysis. The number of components involved simply prevented any worthwhile shortcuts.
The first above identified invention (Ser. No. 09/597,433) automatically derives a logic cone of the relevant cells of the IC which make up the critical signal path leading to the output signal failure. This prior invention greatly facilitates circuit analysis by isolating only those relevant logic cells which may contribute to the failure or malfunction of the IC. However, the circuit analyst must still work through all the logic cells of the automatically derived logic cone in order to isolate the malfunction. Working through the automatically derived cone involves significant effort, although the amount of effort is greatly reduced over the common techniques used prior to this previous invention. Under circumstances where multiple output signals fail from an IC, the tracing task is further complicated because a different, automatically-generated logic cone will typically exist for each of the failed output signals. The circuit analyst must trace each of the logic cones individually, and the fact that multiple different cones exist simultaneously for simultaneously failed output signals increases the number of logic cells which must be individually analyzed, even when the logic cone is automatically generated by use of the prior invention. Thus, in the circumstance of multiple failing output signals from an IC, isolating the fault or faults within the IC may still be a relatively time-consuming and complicated task, even when simplified by use of the previous invention.
These and other considerations have given rise to the present invention.
One aspect of the present invention relates to a new and improved methodology for quickly identifying only those logic cells and their connectivity points or nodes within the IC which are relevant to the functionality or an error in the IC, arising from multiple failing output signals during operation of the IC. As a result, a failed logic cell which is commonly responsible for all of the multiple failed output signals may be quickly identified. Another aspect of the present invention allows the approximate location of the failure point on an IC to be rapidly and automatically identified at or near the convergence of multiple rearwardly-expanding groups or cones of logic cells which are responsible for the critical signal paths involved in the multiple failed output signals. The convergence point of the multiple logic cones identifies or implicates those logic cells and/or their connectivity which cause a common failure of all of the multiple output signals. As a consequence the test engineer need not manually and mentally evaluate each of the automatically generated logic cones by itself to individually identify failure locations. This feature of the invention minimizes the number of logic cells which must be considered, reduces the amount of time required for debugging or understanding the circuit, and reduces the necessity of tracing the logic cells and nodes backwards in the logic cone schematic while minimizing the risks of errors resulting from the manual tracing process itself. The actual number of steps involved in debugging and understanding the circuit are potentially reduced. In general, the present invention facilitates a more rapid and efficient analysis of new semiconductor chips and circuits, and does so under circumstances where an extensive knowledge of the underlying circuit design is not required for efficient analysis.
To achieve these and other aspects, the present invention involves a method of identifying failed cells of a plurality of connected logic cells in an IC having a plurality of output signal pads upon which pad output signals are supplied. The logic cells and waveforms from the logic cells are described by using a simulation tool. The waveforms include input and output waveforms to and from each logic cell, and the output waveform from the logic cell connected to the output signal pad constitutes the pad output signal. The simulation tool describes a waveform transition and a transition time point when the transition occurs. The method comprises the steps of selecting an output waveform and a transition time point of the selected output waveform delivered from a logic cell connected to an output pad, identifying a predictive input waveform and a transition time of the predictive input waveform to the selected logic cell which causes the transition of the output signal from the selected logic cell at the selected transition time, identifying a predictive logic cell connected to the selected logic cell which supplies the output waveform to the selected logic cell which constitutes the previously identified predictive input waveform, and performing at least one new repetition of these steps to accomplish the selecting and identifying steps under circumstances where the predictive logic cell identified in a previous repetition becomes the selected logic cell for the new repetition and the transition time point of the predictive input waveform to the selected logic cell of the previous repetition becomes the selected transition time of the output waveform of the selected logic cell for the new repetition. In addition, method of the present invention includes the steps of defining a logic cone formed from each of the logic cells selected and identified by performing the repetitions, selecting the pad output signal from an output pad as the output waveform for performing the repetitions to define the logic cone, selecting different pad output signals to define different logic cones from the different output pads from which the pad output signals are selected, and identifying the logic cells which are common to the different logic cones.
The common logic cells and their connectivity points or nodes at the convergence of the different logic cones represents the location the likely location of a failure in the IC. The automatic identification of these common cells identifies the probable location of a fault, thereby avoiding the need to manually and mentally evaluate each of the automatically generated logic cones by itself. The number of logic cells which must be considered is reduced, as well as the amount of time required for debugging or understanding the circuit. An extensive knowledge of the underlying circuit design is not required for efficient circuit analysis.
Other preferred aspects of the method of the present invention involve displaying a schematic diagram of the selected and predictive logic cells which are common to the different logic cones, preferably by using a conventional schematic viewing tool and a conventional waveform viewing tool.
Further preferable steps of the present invention involve creating at least one file of the information for each logic cell of the circuit, the information of each logic cell file including information which describes the state of the output waveform at each output waveform transition, the time of each output waveform transition, the predictive input waveform, and the transition time of the predictive input waveform which results in the output waveform transition; creating a logic cone file for each different logic cone, where each logic cone file includes the logic cell files of information of each logic cone; and searching the logic cone files for a plurality of different logic cones to identify common logic cells within the plurality of different logic cone files. At least some of the logic cones may include a synchronous logic cell.